The present invention relates to a driving method and a plasma display apparatus of a three-electrode AC type plasma display panel.
A plasma display apparatus (PDP apparatus) has been put to practical use as a plane display. A description is given below with an example of a three-electrode AC type plasma display panel.
FIG. 1 is a diagram that shows the structure of a normal plasma display panel. As shown schematically, on a substrate 1, plural X (first) electrodes X1, X2, . . . , and Y (second) electrodes Y1, Y2, . . . that extend in one direction are arranged adjacently by turns and plural address electrodes A are further arranged in the direction perpendicular to that of the X electrodes and the Y electrodes. Between the address electrodes, stripe-shaped ribs 2 that extend along the address electrodes are formed. Normally, the X electrodes and the Y electrodes are formed on one of two substrates, the address electrodes are formed on the other substrate, the two substrates are arranged in such a way as to oppose each other, and a gas for discharge is sealed in into a space between them. Display cells are formed at the crossings of pairs of the X electrodes and the Y electrodes, that is, the pair of X1 and Y1, the pair of X2, Y2, . . . and the address electrodes A. Display lines L1, L2, . . . , are, therefore, formed in correspondence with the pairs of the X electrodes and the Y electrodes, that is the pair of X1 and Y1, the pair of X2 and Y2, . . . , as shown schematically.
FIG. 2 is a block diagram that shows the general structure of a conventional PDP apparatus, that uses a plasma display panel 10, shown in FIG. 1. As shown schematically, the PDP apparatus comprises an address driver (a third drive circuit) 11 that selectively applies a voltage to the address electrode A, a Y electrode drive circuit (a second drive circuit) 12 that drives the Y electrode, an X electrode drive circuit (a first drive circuit) 16 that drives the X electrode, and a control circuit 19. The Y electrode drive circuit 12 comprises a scan driver 13 that generates a scan pulse to be applied sequentially to the Y electrode during the address period, a sustain pulse circuit 14 that generates a sustain pulse to be applied sequentially to the Y electrode during the sustain discharge period, and a reset/address voltage generation circuit 15 that generates a voltage to be applied commonly to the Y electrode during the reset period and that except for the scan pulse to be applied commonly to the Y electrode during the address period. The X electrode drive circuit 16 comprises a sustain pulse circuit 17 that generates a sustain pulse to be applied commonly to the Y electrode during the sustain discharge period and a reset/address voltage generation circuit 18 that generates a voltage to be applied commonly to the X electrode during the reset period and the address period.
FIG. 3 is a diagram that shows the drive waveforms of the PDP apparatus in FIG. 2. As shown schematically, one action cycle comprises a reset period during which all the display cells are brought into a uniform state, an address period during which a display cell to be lit is selected, and a sustain discharge period during which only the selected display cell is lit. The luminance is determined by the number of sustain pulses in the sustain discharge period. When the frequency of the sustain pulse is constant, the number of sustain pulses is in proportion to the length of the sustain discharge period. The PDP apparatus is only able to select the lit or unlit state of each display cell, therefore, when an image with gradation is displayed, one display field is constructed by plural subfields which have the action cycle shown in FIG. 3, and the length of the sustain discharge period of which differs at least in part, and the subfields to be lit are selected for each display cell.
In the reset period, the address driver 11 applies 0V to all the address electrodes and the reset/address voltage generation circuit 18 of the X electrode drive circuit 16 and the reset/address voltage generation circuit 15 of the Y electrode drive circuit 12 apply the voltages as shown in FIG. 3 to all the X electrodes and all the Y electrodes. The reset period is composed of a write portion that applies a positive voltage to the Y electrode as well as applying a negative voltage to the X electrode and an erase portion that applies a negative voltage to the Y electrode as well as applying a positive voltage to the X electrode. In the write portion, after the negative voltage applied to the X electrode is changed gradually, a positive voltage that changes gradually is applied to the Y electrode, and wall charges are formed in all the display cells by a slight discharge. In the erase portion, the voltage applied to the X electrode is switched to a positive one and simultaneously a negative voltage that changes gradually is applied to the Y electrode so that the wall charges in all the display cells are erased or adjusted to a certain amount by a slight discharge. In the address period, in a state in which a voltage Vx is being applied to all the X electrodes, the scan pulse is applied sequentially to the Y electrode and the address pulse that corresponds to the display data is applied selectively to the address electrode in synchronization with the scan pulse. An address discharge is caused to occur in the cell at the crossing of the Y electrode to which the scan pulse is applied and the address electrode to which the address pulse is applied, and no discharge is caused to occur in the cell at the crossing of the address electrode to which the address pulse is not applied. Wall charges are formed in the cell in which the address discharge is caused to occur and each display cell is brought into a state that corresponds to the display data. In the sustain discharge period, in a state in which 0V is being applied to the address electrode, a sustain pulse that change between 0V and a voltage Vs is applied alternately to the Y electrode and the x electrode. A sustain discharge is caused to occur in the cell in which wall charges are accumulated during the address period because the voltage due to the wall charges is added to the sustain pulse and the discharge start voltage is exceeded, and no sustain discharge is caused to occur in the cell in which no wall charge is accumulate during the address period. The wall charges are formed alternately on the Y electrode and the X electrode by the sustain discharge, and the sustain discharge continues as long as the sustain pulse is being applied.
The typical method of the PDP apparatus is described above as an example, but various kinds of methods are put to practical use and there are many examples of modifications.
Recently, the display apparatus has been highly improved in capacity and resolution, and the plasma display panel has increased the number of lines from approximately 500 to 1,000. Moreover, it is required that the number of levels in gradation should be increased and that the number of subfields should be increased to avoid the false contour when a motion video is displayed, which is inherent in a device that performs display using subfields. If the number of display lines is increased, the number of times an addressing is performed is increased and the time to be assigned to one address action, that is, the width of the scan pulse becomes shorter. If the number of subfields is increased, the time to be assigned to the address period becomes shorter and it is necessary to shorten the width of the scan pulse. If, however, the width of the scan pulse is shortened, a problem occurs in that no address discharge is caused to occur, even though an address pulse is applied, and display data cannot be written correctly.
One of the methods to solve the problem is the so-called dual scan method, in which the address period is halved by dividing the address electrode horizontally and performing the address action simultaneously in the upper screen and the lower screen. This method, however, brings about a problem that two address drivers to drive the address electrode are required, resulting in the disadvantage of a higher cost.
Another method has been proposed in which the address of one display line is performed at a high-speed. For example, sufficient space charges that are generated by the reset discharge during the reset period are made to remain, thereby the address discharge is made more likely to occur and the delay time of the address discharge is shortened. It is, however, necessary to increase the intensity of the reset discharge in order to generate a sufficient amount of space charges and a problem is caused in that the quality of display is degraded because the entire surface light emission intensity due to the reset discharge increases and the contrast is degraded.
Moreover, there is another method in which the voltage to be applied during the address discharge is increased to promote the development of the discharge and the address discharge is completed in a short time. This method, however, brings about various problems of such as crosstalk between the neighboring cells and lack of control of the discharge.
On the other hand, Japanese unexamined Patent Publication (Kokai) No. 9-311661 has disclosed the method in which the absolute value of the voltage of the scan pulse to be applied to the Y electrode is reduced by providing the scan driver also to the X electrode drive circuit and by applying the scan pulse of the opposite polarity to the X electrode in synchronization with the application of scan pulse to the Y electrode during the address period. The advantage of this method lies in the fact that the withstand voltage of the drive circuit can be reduced, but the same problem, as described above, may occur when the width of the scan pulse becomes short.
The address discharge is started when the address pulse is applied to the address electrode and the scan pulse is applied to the Y electrode, but an amount of wall charges enough to cause the sustain discharge to occur is not generated only by the discharge between the address electrode and the Y electrode. A high voltage, therefore, is applied to the X electrode so that the discharge caused to occur between the address electrode and the Y electrode causes the discharge to occur between the X electrode and the Y electrode, and the discharge between the X electrode and the Y electrode is completed after it develops to generate the wall charges necessary for the sustain discharge. If the time required for the series of these actions is too short, the discharge between the X electrode and the Y electrode does not develop even though the discharge between the address electrode and the Y electrode is caused to occur, and a state is brought about in which a sufficient amount of wall charges is not formed (a state of imperfect address discharge), therefore, it seems that the sustain discharge is not caused to occur. The term “development of the discharge” described above is used because a certain length of time is required to generate a sufficient amount of wall charges after the discharge is completed.
As described above, the problem lies in the fact that the width of the address pulse needs to be shortened to increase the number of display lines and to improve the gradation reproduction, but this adversely affects the stable actions.